1. Technical Field
The present invention relates generally to semiconductor integrated circuit processing, and in particular to electrostatic discharge protection for semiconductor device. Still more particularly, the present invention relates to a method and apparatus for providing electrostatic discharge protection in complimentary metal oxide semiconductor integrated circuits.
2. Description of the Related Art
An electrostatic discharge is basically more or less a sudden violent redistribution of electrons between bodies, such that in their new special equilibrium position, the electrons end up as far away from each other as they could possibly get. The charges always position themselves outside the skin of a conductive body because of the repulsion between the charges.
Whenever movement occurs, a static charge may be produced. Electrostatic discharge (ESD) is caused by the rapid flow of charge between two objects. Voltages as low as 200 volts can damage the vices. Typically, a person feels ESD at greater than 3,000 volts. ESD may cause gate oxide breakdown, junction spiking, and latch-up in various integrated circuit devices.
It has been shown that voltage potentials up to 28 kV can be generated and discharged in less than 10 nanosecond through an IC device when handled by a person. Electrostatic charge can also be accumulated on pin of the lead frame of a packaged IC device during shipping, storage or while being integrated into an electronic system which is discharged when another pin is grounded. The discharge of the high electrostatic voltage can result in a current of about two amperes. The high current must flow through the IC device when another pin or pad is grounded. MOS devices are particularly susceptible to discharge of the electrostatic charge because the thin gate oxide can be easily ruptured by the voltage induced by the high current.
ESD events can and do happen to semiconductor devices during normal handling or operating procedures associated with transportation, manufacturing, and testing. A device, which suffers from damage, may fail to operate correctly.
CMOS integrated circuit devices are vulnerable to electrostatic discharge (ESD) induced failure. ESD events or spikes are typically short-duration, high-voltage electrical pulses that are caused, for example, by discharge of a static charge. ESD causes failure of a MOS integrated circuit device by overheating components due to overcurrent, breakdown of thin oxide, or other conditions. ESD can damage or destroy integrated circuit devices unless measures are taken to reduce ESD effects on the input pins and output pins of the devices. Various techniques have been used to self-protect output buffers or other input-output nodes against ESD failures. Some of these measures include diode clamps, lateral punch-through devices, and guard ring collectors around and input-output bonding pad. These circuits are reasonably effective for protecting input circuits, but are less effective for protecting output circuits from high transient voltages.
These internal ESD structures are employed typically to bypass over-voltage events to either a power supply voltage, such as VCC, or a lower power supply voltage, such as VSS, or ground. Metal oxide semiconductor (MOS) and complimentary metal oxide semiconductor (CMOS) devices within gate oxides are particularly susceptible to ESD events.
All integrated circuit (IC) devices are sensitive to ESD to some degree. However, as IC devices are made smaller, ESD damage is more likely to occur and render the device inoperable in response to an ESD event. Particularly susceptible are MOS and CMOS devices with thin gate oxides.
The need for ESD protection in IC devices that can handle the high current produced by an ESD event has been recognized for many years. However, it is typical that ESD protection circuits are designed to provide protection against electrostatic charge levels of between 500 volts to 3.0 kilovolts because once the IC device has been inserted into a system, the need for ESD protection is minimized since most such systems generally incorporate sophisticated ESD protection. However, prior to insertion, IC devices are particularly vulnerable to ESD pulses applied to the IC device""s pins or pads.
As CMOS integrated circuits are scaled to thinner oxides, the input/output (I/O) circuitry is becoming more sensitive to ESD. Salicided source/drain defusions tend to further aggravate this ESD sensitivity as output transistors have less series resistance to limit the current through any given cross section of the device.
As the output data path transistors, transistors actually involved in chip-to-chip data transmission, become more and more ESD sensitive, it is increasingly common to deploy a dummy device of some sort to discharge ESD pulse. The intent is to alleviate all ESD-driven constraints on the output transistor by having a separate element disperse the charge in the ESD pulse.
One problem with this approach is finding an ESD protection element, which will always trigger before the data path transistor. Numerous elements have been employed including metal oxide semiconductor field effect transistors (MOSFETs), silicon controlled rectifiers (SCRs), zener diodes, and bipolar devices. In almost every case, additional process steps are required to ensure that the protection device has a lower breakdown or trigger voltage compared with the data path transistor. The additional process steps increase the time and increase the complexity of manufacturing integrated circuits.
Therefore, it would be advantageous to have an improved method for manufacturing an ESD protection element that does not require additional process steps to set a lower breakdown voltage compared to that of a data path transistor.
The present invention provides a method and apparatus for manufacturing an electrostatic discharge protection device. A first gate structure and a second gate structure are formed for the electrostatic device and a data path transistor. A first lightly doped drain and a second lightly doped drain is formed for the electrostatic discharge protection device. A third lightly doped drain and a fourth lightly doped drain is formed for a data path transistor, wherein the first lightly doped drain and the second lightly doped drain have a higher doping level relative to the third lightly doped drain and the fourth lightly doped drain.